(1) Field of the Invention
This invention relates to semiconductor integrated circuit devices, and more particularly relates to a method for making dynamic random access memory (DRAM) crown capacitors with improved physical strength. The process is particularly useful for crown capacitors for the next generation of DRAM circuits with minimum feature sizes of 0.18 micrometer (um) and less. The invention uses a protective interlevel dielectric (ILD) structure between capacitors while utilizing most of the other surface (>50%) for increasing the capacitance.
(2) Description of the Prior Art
Dynamic random access memory (DRAM) circuits (devices) are used extensively in the electronics industry, and more particularly in the computer industry for storing data in binary form (1s and 0s) as charge on a storage capacitor. These DRAM device are made on a semiconductor substrate (or wafer), and then the substrate is diced to form the individual DRAM circuits (or chips). Each DRAM circuit (chip) consists in part of an array of individual memory cells that store binary data (bits) as electrical charge on the storage capacitors. Further, the information is stored and retrieved from the storage capacitors by means of switching on or off a single access transistor (via word lines) in each memory cell using peripheral address circuits, while the charge stored on the capacitors is sensed via bit lines and by read/write circuits formed on the peripheral circuits of the DRAM chip.
Since the capacitor area is limited to the cell size, in order to accommodate the multitude of cells on the DRAM chip, it is necessary to explore alternative methods for increasing the capacitance while decreasing the lateral area that the capacitor occupies on the substrate surface. In recent years the method of choice is to build stacked capacitors in the vertical direction over the access transistors within each cell area to increase the capacitance of the individual capacitors by increasing the capacitor area in the vertical direction. This provides increased latitude in capacitor design while reducing the cell area.
However, as the minimum feature size for future product is reduced to 0.18 um or less, the ratio of the bottom width to the height of the crown capacitor is dramatically reduced, and the wall of the capacitor bottom electrode is also much thinner. Therefore, it is difficult to form these fragile freestanding capacitor bottom electrodes without resulting in damage during subsequent processing.
To better understand this problem, FIG. 1 shows a crown capacitor on a substrate 10 before removing the interlevel dielectric layer. The partially completed devices, such as the shallow trench isolation and the pass transistors on the substrate, are not depicted to simplify the drawings The method for making the crown capacitors includes depositing a first insulating layer 12 over the partially completed device areas on the substrate 10. Openings 2 for capacitor node contacts are etched in the insulating layer 12 and filled with a conducting material, such as doped polysilicon, tungsten, and the like to form the node contacts 14. A thick second insulating layer 16 (ILD) is deposited and openings 4 are etched over the node contacts 14 for the capacitor bottom electrodes. Then a conformal conducting layer 20 is deposited and polished back to form the bottom electrodes 20 for the capacitors. By retaining the second insulating layer 16, only the inner surface of the conducting layer 20 is used to make the capacitor (referred to as an inner-crown capacitor). However, the available are for making the capacitor is substantially reduced since the outside surface area of the bottom electrode is not used for capacitance.
As shown in FIG. 2 the second insulating layer 16 is completely removed to form freestanding bottom electrodes 20 for the crown capacitors. The capacitor area is substantially increased. However, for future DRAMs having minimum feature sizes less than 0.18 um, the ratio of the height over the width at the base is substantially increased. Because of the extreme height and narrow base, the bottom electrode structure is not sturdy, and is prone to damage during subsequent processing.
One method of reducing the process damage is to partially blanket etch back the ILD layer 16 to provide additional support at the base of the capacitor bottom electrode 20, as shown in FIG. 3. Unfortunately, due to non-uniform loading effects and etching variations across the wafer, non-uniform etching of the ILD layer between the closely spaced bottom electrodes 20 results in poor etch uniformity between the capacitor bottom electrode sand across the wafer, and results in unacceptably large variations in capacitance among individual memory cells when the capacitors are completed.
Numerous methods of making stacked capacitors with vertical structures to increase capacitance while increasing the packing density of the cells have been reported in the literature. For example, U.S. Pat. No. 6,130,128 to Lin and U.S. Pat. No. 6,187,625 B1 to Lin, et a1. both describe a method for fabricating a crown capacitor having double sidewalls using a freestanding bottom electrode, as shown in FIG. 2K of both patents. Huang in U.S. Pat. No. 6,187,624 B1 describes a method for making closely spaced capacitors in adjacent recesses. The process forms the capacitor bottom electrode on the inner surface of the recess only. The method is for making closely spaced capacitors with a low-dielectric-constant material between capacitors to reduce coupling. In U.S. Pat. No. 6,180,483 B1 to Linliu describes a method for making multiple crown capacitors. The method relies upon forming freestanding bottom electrodes, as shown in FIG. 1D. None of the above cited references addresses the problem of bottom-electrode damage during subsequent processing.
However, there is till a need in the semiconductor industry to provide crown capacitors having increased uniform capacitance among individual memory cells while reducing the susceptibility to process damage subsequent to making the capacitor bottom electrodes.